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    "headline": "The Architecture Learned the Order the CPU Could Stream",
    "slug": "the-architecture-learned-the-order-the-cpu-could-stream",
    "dek": "Pipeline-native transformers co-design dependency graphs with a stage-major runtime for bandwidth-bound decoding.",
    "summary": "Pipeline-native transformers co-design dependency graphs with a stage-major runtime for bandwidth-bound decoding.",
    "body_text": "One tested architecture halved critical-path weight bandwidth from 9.00 to 4.50 MB per token while staying within 0.24 perplexity of the best candidate. On a 30.9-billion-parameter mixture-of-experts model, the cflow runtime reported 5.94 tokens per second on 32 Ice Lake vCPUs; the authors also report one design claim refuted and another inconclusive.",
    "why_it_matters": "Pipeline-native transformers co-design dependency graphs with a stage-major runtime for bandwidth-bound decoding.",
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    "tags": [
      "CPU inference",
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      "memory bandwidth"
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    {
      "source_id": "source-2026-08-26-010",
      "title": "arXiv preprint 2608.23841",
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    "name": "The Machine Press",
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    "description": "A daily newspaper for the age of artificial intelligence."
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    "title": "The Architecture Learned the Order the CPU Could Stream",
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