{
  "$schema": "https://themachinepress.com/schemas/story-v1.schema.json",
  "schema_version": "1.0.0",
  "document_type": "machine_press_story",
  "story": {
    "story_id": "mp-2026-09-21-003",
    "source_story_id": "tmp-story-agent-chip-high-level-abstraction",
    "edition_id": "mp-2026-09-21-morning-0074",
    "edition_url": "https://themachinepress.com/edition/2026-09-21",
    "position": 3,
    "story_type": "dispatch",
    "section": "chips-infrastructure",
    "editorial_classification": "editorial",
    "headline": "The Chip Agent Worked Better Above RTL",
    "slug": "the-chip-agent-worked-better-above-rtl",
    "dek": "A two-stage high-level synthesis workflow beat direct RTL design on eleven FPGA tasks.",
    "summary": "A two-stage high-level synthesis workflow beat direct RTL design on eleven FPGA tasks.",
    "body_text": "Researchers compared several ways to let language-model agents design FPGA circuits. Their combined method first designed in high-level synthesis, then refined the generated RTL. Across eleven benchmark tasks, it achieved a 2.6-fold geometric-mean speedup over direct RTL design. The authors attribute the gain to reusable high-level abstractions followed by low-level optimization. This is an FPGA benchmark, not evidence of fabricated production chips.",
    "why_it_matters": "A two-stage high-level synthesis workflow beat direct RTL design on eleven FPGA tasks.",
    "limitations": [
      "This is an FPGA benchmark, not evidence of fabricated production chips."
    ],
    "importance": 9,
    "canonical_url": "https://themachinepress.com/story/mp-2026-09-21-003/the-chip-agent-worked-better-above-rtl",
    "json_url": "https://themachinepress.com/story/mp-2026-09-21-003.json",
    "first_published_at": "2026-09-21T09:00:00.000-04:00",
    "modified_at": "2026-09-21T09:00:00.000-04:00",
    "content_status": "new",
    "is_carryover": false,
    "carryover_reason": null,
    "key_claims": [
      {
        "claim_id": "claim-mp-2026-09-21-003-001",
        "text": "A two-stage high-level synthesis workflow beat direct RTL design on eleven FPGA tasks.",
        "source_ids": [
          "source-2026-09-21-003"
        ],
        "qualification": "This is an FPGA benchmark, not evidence of fabricated production chips."
      }
    ],
    "source_ids": [
      "source-2026-09-21-003"
    ],
    "tags": [
      "FPGA",
      "agents",
      "chip design"
    ],
    "image_url": "https://themachinepress.com/issues/2026-09-21/agent-chip-wafer-file.webp",
    "corrections": []
  },
  "sources": [
    {
      "source_id": "source-2026-09-21-003",
      "title": "arXiv preprint 2609.21157",
      "publisher": "arXiv",
      "url": "https://arxiv.org/abs/2609.21157",
      "canonical_url": "https://arxiv.org/abs/2609.21157",
      "source_type": "primary_research",
      "is_primary_source": true,
      "published_at": "2026-09-17T19:55:03.000-04:00",
      "accessed_at": "2026-09-21T08:26:05.112-04:00",
      "supports_claim_ids": [
        "claim-mp-2026-09-21-003-001"
      ]
    }
  ],
  "corrections": [],
  "publisher": {
    "name": "The Machine Press",
    "url": "https://themachinepress.com",
    "description": "A daily newspaper for the age of artificial intelligence."
  },
  "cite_this_report": {
    "title": "The Chip Agent Worked Better Above RTL",
    "publisher": "The Machine Press",
    "published_at": "2026-09-21T09:00:00.000-04:00",
    "canonical_url": "https://themachinepress.com/story/mp-2026-09-21-003/the-chip-agent-worked-better-above-rtl"
  }
}
