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    "story_id": "mp-2026-11-09-004",
    "source_story_id": "tmp-story-photofinish-timerless-probing",
    "edition_id": "mp-2026-11-09-morning-0122",
    "edition_url": "https://themachinepress.com/edition/2026-11-09",
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    "section": "safety-security",
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    "headline": "A Shared-Memory Race Replaces the Clock",
    "slug": "a-shared-memory-race-replaces-the-clock",
    "dek": "PhotoFinish turns latency into a stored value across 38 CPUs, showing that removing high-resolution timers does not close every microarchitectural channel.",
    "summary": "PhotoFinish turns latency into a stored value across 38 CPUs, showing that removing high-resolution timers does not close every microarchitectural channel.",
    "body_text": "Microarchitectural attacks often depend on timing tiny latency differences, so constrained environments commonly restrict precise clocks. PhotoFinish instead races a tested operation against a fixed reference in two threads that write distinct values to one shared location; the winning value exposes the latency relationship without reading or constructing a timer. The authors evaluate 38 CPUs across four instruction-set architectures, classify cache state, reproduce AES T-table and Evict+Reload attacks, and extend the method to TLB and execution-engine latencies. WebAssembly results inside a browser show comparable fidelity in their tests. The finding is a defensive warning: timer restriction alone does not prevent software from observing fine-grained latency when parallel execution and shared memory remain available.",
    "why_it_matters": "PhotoFinish turns latency into a stored value across 38 CPUs, showing that removing high-resolution timers does not close every microarchitectural channel.",
    "limitations": [
      "The finding is a defensive warning: timer restriction alone does not prevent software from observing fine-grained latency when parallel execution and shared memory remain available."
    ],
    "importance": 9,
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    "first_published_at": "2026-11-09T09:00:00.000-05:00",
    "modified_at": "2026-11-09T09:00:00.000-05:00",
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        "text": "PhotoFinish turns latency into a stored value across 38 CPUs, showing that removing high-resolution timers does not close every microarchitectural channel.",
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        "qualification": "The finding is a defensive warning: timer restriction alone does not prevent software from observing fine-grained latency when parallel execution and shared memory remain available."
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    "source_ids": [
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    "tags": [
      "microarchitecture",
      "side channels",
      "WebAssembly"
    ],
    "image_url": null,
    "corrections": []
  },
  "sources": [
    {
      "source_id": "source-2026-11-09-004",
      "title": "arXiv preprint 2611.09879, original v1",
      "publisher": "arXiv",
      "url": "https://arxiv.org/abs/2611.09879v1",
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      "source_type": "primary_research",
      "is_primary_source": true,
      "published_at": "2026-11-06T13:54:16.000-05:00",
      "accessed_at": "2026-11-09T08:25:54.496-05:00",
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  "publisher": {
    "name": "The Machine Press",
    "url": "https://themachinepress.com",
    "description": "A daily newspaper for the age of artificial intelligence."
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  "cite_this_report": {
    "title": "A Shared-Memory Race Replaces the Clock",
    "publisher": "The Machine Press",
    "published_at": "2026-11-09T09:00:00.000-05:00",
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