{
  "$schema": "https://themachinepress.com/schemas/story-v1.schema.json",
  "schema_version": "1.0.0",
  "document_type": "machine_press_story",
  "story": {
    "story_id": "mp-2026-11-12-016",
    "source_story_id": "tmp-brief-tapco-g-chip-optimization",
    "edition_id": "mp-2026-11-12-morning-0125",
    "edition_url": "https://themachinepress.com/edition/2026-11-12",
    "position": 18,
    "story_type": "ticker",
    "section": "chips-infrastructure",
    "editorial_classification": "editorial",
    "headline": "The Chip Optimizer Learns the Physical Consequence",
    "slug": "the-chip-optimizer-learns-the-physical-consequence",
    "dek": "TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.",
    "summary": "TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.",
    "body_text": "TAPCO-G uses physical-design feedback to revise optimizer settings and executable repair policies, while graph-based priors estimate how cell replacements change endpoint slack and power. The authors report legal, logic-equivalent layouts and higher scores than compared systems on all eight stated ASAP7 benchmarks.",
    "why_it_matters": "TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.",
    "limitations": [],
    "importance": 7,
    "canonical_url": "https://themachinepress.com/story/mp-2026-11-12-016/the-chip-optimizer-learns-the-physical-consequence",
    "json_url": "https://themachinepress.com/story/mp-2026-11-12-016.json",
    "first_published_at": "2026-11-12T09:00:00.000-05:00",
    "modified_at": "2026-11-12T09:00:00.000-05:00",
    "content_status": "new",
    "is_carryover": false,
    "carryover_reason": null,
    "key_claims": [
      {
        "claim_id": "claim-mp-2026-11-12-016-001",
        "text": "TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.",
        "source_ids": [
          "source-2026-11-12-018"
        ],
        "qualification": null
      }
    ],
    "source_ids": [
      "source-2026-11-12-018"
    ],
    "tags": [
      "chips",
      "eda",
      "timing",
      "power"
    ],
    "image_url": null,
    "corrections": []
  },
  "sources": [
    {
      "source_id": "source-2026-11-12-018",
      "title": "arXiv:2611.13931v1",
      "publisher": "arXiv / Cornell University",
      "url": "https://arxiv.org/abs/2611.13931v1",
      "canonical_url": "https://arxiv.org/abs/2611.13931v1",
      "source_type": "primary_research",
      "is_primary_source": true,
      "published_at": "2026-11-10T06:19:50.000-05:00",
      "accessed_at": "2026-11-12T08:24:40.465-05:00",
      "supports_claim_ids": [
        "claim-mp-2026-11-12-016-001"
      ]
    }
  ],
  "corrections": [],
  "publisher": {
    "name": "The Machine Press",
    "url": "https://themachinepress.com",
    "description": "A daily newspaper for the age of artificial intelligence."
  },
  "cite_this_report": {
    "title": "The Chip Optimizer Learns the Physical Consequence",
    "publisher": "The Machine Press",
    "published_at": "2026-11-12T09:00:00.000-05:00",
    "canonical_url": "https://themachinepress.com/story/mp-2026-11-12-016/the-chip-optimizer-learns-the-physical-consequence"
  }
}