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Six Light Modes Shared One Chip Without Crowding
A hierarchical transformation addressed arbitrary supermodes and carried an aggregate 1.2 terabits per second in a silicon demonstration.

Summary
A hierarchical transformation addressed arbitrary supermodes and carried an aggregate 1.2 terabits per second in a silicon demonstration.
The reported design uses a second-order discrete supersymmetric transformation to excite and extract selected supermodes while preserving large, even index spacing. Six-mode multiplexers built on silicon and silicon nitride showed insertion losses below 2.6 decibels and crosstalk below minus 11.1 decibels over 100 nanometers. A silicon device transmitted an aggregate 1.2 terabits per second below the stated error-correction threshold.
Why it matters
A hierarchical transformation addressed arbitrary supermodes and carried an aggregate 1.2 terabits per second in a silicon demonstration.
Limits and context
No additional limitation was separately recorded.
Key claims
A hierarchical transformation addressed arbitrary supermodes and carried an aggregate 1.2 terabits per second in a silicon demonstration.
Evidence: source-2026-08-12-008
Sources
- arXiv preprint 2608.11099arXiv · primary research
Corrections
No corrections have been recorded for this story.