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The Error-Corrected Architecture Did More Than Remember
A 98-qubit trapped-ion processor demonstrated protected logic and an interface between two codes without postselection.
Summary
A 98-qubit trapped-ion processor demonstrated protected logic and an interface between two codes without postselection.
Using Quantinuum Helios, the team tests the principal pieces of a C4-Helix architecture aimed at early fault-tolerant computation. Repeated correction produced an estimated 4.6×10^-5 error per logical qubit per cycle, while actively corrected two-logical-qubit Clifford operations reached 2.8×10^-4. A chain-map interface then linked C4-Helix to a distance-five surface code and prepared a heterogeneous three-logical-qubit GHZ state with a reported fidelity lower bound above 99.9%. Each encoded experiment beat its unencoded baseline, though the projected millionth-to-hundred-millionth error regime still depends on better physical fidelity.
Why it matters
A 98-qubit trapped-ion processor demonstrated protected logic and an interface between two codes without postselection.
Limits and context
No additional limitation was separately recorded.
Key claims
A 98-qubit trapped-ion processor demonstrated protected logic and an interface between two codes without postselection.
Evidence: source-2026-09-05-013
Sources
- arXiv preprint 2609.03194arXiv · primary research
Corrections
No corrections have been recorded for this story.