chips infrastructure
The Edge Chip Stopped Choosing Between a Pipeline and Parallel Work
Para-Pipe maps operator concurrency within and across stages, producing Pareto choices for latency, throughput and energy on heterogeneous SoCs.
Summary
Para-Pipe maps operator concurrency within and across stages, producing Pareto choices for latency, throughput and energy on heterogeneous SoCs.
The framework searches how a neural graph should share work across big and little CPU cores, a GPU, DSPs and a dedicated accelerator. On one Amlogic system, throughput-optimized configurations improved average energy efficiency by 11.0 percent over pure pipelining and 23.3 percent over non-pipelined parallel execution. A second automotive-class platform supplied another heterogeneous test. These are measurements on the authors' graphs and devices, not general efficiency guarantees for all edge workloads.
Why it matters
Para-Pipe maps operator concurrency within and across stages, producing Pareto choices for latency, throughput and energy on heterogeneous SoCs.
Limits and context
- These are measurements on the authors' graphs and devices, not general efficiency guarantees for all edge workloads.
Key claims
Para-Pipe maps operator concurrency within and across stages, producing Pareto choices for latency, throughput and energy on heterogeneous SoCs.
Qualification: These are measurements on the authors' graphs and devices, not general efficiency guarantees for all edge workloads.
Evidence: source-2026-09-06-013
Sources
- arXiv preprint 2609.04168arXiv · primary research
Corrections
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