chips infrastructure
The Chip Optimizer Learns the Physical Consequence
TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.
Summary
TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.
TAPCO-G uses physical-design feedback to revise optimizer settings and executable repair policies, while graph-based priors estimate how cell replacements change endpoint slack and power. The authors report legal, logic-equivalent layouts and higher scores than compared systems on all eight stated ASAP7 benchmarks.
Why it matters
TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.
Limits and context
No additional limitation was separately recorded.
Key claims
TAPCO-G combines language-model policy changes with graph priors for timing and power repairs.
Evidence: source-2026-11-12-018
Sources
- arXiv:2611.13931v1arXiv / Cornell University · primary research
Corrections
No corrections have been recorded for this story.